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| N-CHANNEL 600V - 3.3 - 2.6A DPAK/IPAK PowerMESHTM MOSFET Table 1. General Features Type STD2NB60 STD2NB60-1 VDSS 600 V 600 V RDS(on) < 3.6 < 3.6 ID 2.6 A 2.6 A STD2NB60 STD2NB60-1 Figure 1. Package FEATURES SUMMARY TYPICAL RDS(on) = 3.3 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED IPAK TO-251 3 2 1 3 1 DPAK TO-252 DESCRIPTION Using the latest high voltage MESH OVERLAYTM process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company's proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/ dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS SWITCH MODE POWER SUPPLIES (SMPS) Figure 2. Internal Schematic Diagram DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE Table 2. Order Codes Part Number STD2NB60T4 STD2NB60-1 Marking D2NB60 D2NB60 Package DPAK IPAK Packaging TAPE & REEL TUBE REV. 2 April 2004 1/11 STD2NB60/STD2NB60-1 Table 3. Absolute Maximum Ratings Symbol VDS VDGR VGS ID ID IDM (1) Parameter Drain-source Voltage (VGS = 0) Drain- gate Voltage (RGS = 20 k) Gate-source Voltage Drain Current (cont.) at TC = 25 C Drain Current (cont.) at TC = 100 C Drain Current (pulsed) Total Dissipation at TC = 25 C Derating Factor Value 600 600 30 2.6 1.6 10.4 50 0.4 4.5 -65 to 150 150 Unit V V V A A A W W/C V/ns C C Ptot dv/dt (2) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Note: 1. Pulse width limited by safe operating area 2. ISD 2.6A, di/dt 200 A/s, VDD V(BR)DSS, Tj TJMAX Table 4. Thermal Data Symbol Rthj-case Rthj-amb Tl Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max Value 2.5 100 275 Unit C/W C/W C Maximum Lead Temperature For Soldering Purpose Table 5. Avalanche Characteristics Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, < 1%) Single Pulse Avalanche Energy (starting Tj = 25 C; ID = IAR; VDD = 50 V) Max Value 2.6 80 Unit A mJ 2/11 STD2NB60/STD2NB60-1 ELECTRICAL CHARACTERISTICS (Tcase = 25C unless otherwise specified) Table 6. Off Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) IGSS Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A VGS = 0 VDS = Max Rating VDS = Max Rating Tc = 125 C VGS = 30 V Min. 600 1 50 100 Typ. Max. Unit V A A nA Table 7. On (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS; ID = 250 A VGS = 10V; ID = 1.6 A Min. 3 Typ. 4 3.3 Max. 5 3.6 Unit V Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 % Table 8. Dynamic Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max; ID = 1.6 A VDS = 25 V; f = 1 MHz; VGS = 0 Min. 1.2 Typ. 2 400 57 7 520 77 9 Max. Unit S pF pF pF Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 % Table 9. Switching On Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 300 V; ID = 1.6 A; RG = 4.7 VGS = 10 V (see test circuit, Figure 16) VDD = 480 V; ID = 3.3 A; VGS = 10 V Min. Typ. 11 7 15 6.2 5.6 Max. 17 11 22 Unit ns ns nC nC nC Table 10. Switching Off Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 480 V; ID = 3.3 A; RG = 4.7 VGS = 10 V (see test circuit, Figure 18) Min. Typ. 11 13 18 Max. 16 18 25 Unit ns ns ns 3/11 STD2NB60/STD2NB60-1 Table 11. Source Drain Diode Symbol ISD ISDM (1) VSD (2) trr Qrr IRRAM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse RecoveryCharge Reverse RecoveryCharge ISD = 3.3 A; VGS = 0 ISD = 3.3 A; di/dt = 100 A/s VDD = 100 V; Tj = 150 C (see test circuit, Figure 18) 500 2.1 8.5 Test Conditions Min. Typ. Max. 3.3 13.2 1.6 Unit A A V ns C A Note: 1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 % Figure 3. Safe Operating Area Figure 4. Thermal Impedance Figure 5. Output Characteristics Figure 6. Transfer Characteristics 4/11 STD2NB60/STD2NB60-1 Figure 7. Transconductance Figure 8. Gate Charge vs Gate-source Voltage Figure 9. Static Drain-source On Resistance Figure 10. Capacitance Variations Figure 11. Normalized Gate Thresold Voltage vs Temperature Figure 12. Normalized On Resistance vs Temperature 5/11 STD2NB60/STD2NB60-1 Figure 13. Source-drain Diode Forward Characteristics 6/11 STD2NB60/STD2NB60-1 Figure 14. Unclamped Inductive Load Test Circuit Figure 15. Unclamped Inductive Waveforms Figure 16. Switching Times Test Circuits For Resistive Load Figure 17. Gate Charge Test Circuit Figure 18. Test Circuit For Inductive Load Switching And Diode Recovery Times 7/11 STD2NB60/STD2NB60-1 PACKAGE MECHANICAL Table 12. DPAK Mechanical Data Symbol A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0 millimeters Min 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 0.8 1.00 8 0.024 0 Typ Max 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 Min 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 0.039 0 0.024 0.024 0.244 0.260 0.181 0.398 inches Typ Max 0.094 0.043 0.009 0.035 0.213 Figure 19. DPAK Package Dimensions P032P_B Note: Drawing is not to scale. 8/11 STD2NB60/STD2NB60-1 Table 13. IPAK Mechanical Data Symbol A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.63 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 millimeters Min 2.2 0.9 0.7 0.64 5.2 Typ Max 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 Min 0.086 0.035 0.027 0.025 0.204 inches Typ Max 0.094 0.043 0.051 0.031 0.212 0.033 Figure 20. IPAK Package Dimensions H C A C2 L2 D B3 B6 A1 L = B2 = 3 B5 G E = = L1 1 2 B A3 0068771-E Note: Drawing is not to scale. 9/11 STD2NB60/STD2NB60-1 REVISION HISTORY Table 14. Revision History Date March-1998 14-Apr-2004 Revision 1 2 First Issue Stylesheet update. No content change. Description of Changes 10/11 STD2NB60/STD2NB60-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 11/11 |
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